A sense amplifier is a circuit that is used in memory device designs to sense small voltage differentials between two input signals, for example, such as the complementary bit-lines connected to a memory cell. Certain types of regenerative sense amplifier circuits contain circuit nodes that are highly sensitive to electrical noise due to the very high gain nature of some designs. These nodes, if not properly addressed, can cause anything from functional failure to out of specification performance. Accordingly, these nodes must be controlled in such a way as to reduce the susceptibility of faulty operation without adversely impacting the performance characteristics of the sense amplifier function.
FIG. 1 illustrates a schematic diagram of a conventional latch-type, cross-coupled sense amplifier circuit 10 for sensing voltage differentials on a pair of complementary bit-lines. The latch consists of the inverter formed by PMOS and NMOS transistors M1 and M2, which is cross-coupled with the inverter formed by PMOS and NMOS transistors M3 and M4. The bit-lines 12 and 14 are connected to the input nodes of the data-latch via NMOS transistors M5 and M6. When the sense amplifier enable (SAE) signal 16 is in a low voltage state, the data-latch is coupled to VDD via PMOS transistor M7, and isolated from GROUND via NMOS transistor M8. When SAE 16 changes to a high voltage state, the NMOS transistor M8 is enabled, or turned on, thereby forming a circuit path to GROUND and initiating the data latching operation.
One of the problems with the circuit shown in FIG. 1 is that there is nothing to control the voltage levels at the critical nodes CN1 and CN2 just prior to the activation of the sense amplifier. For example, just prior to the circuit being activated (e.g., when the sense amplifier enable signal (SAE) changes from a low to a high voltage state), the voltage levels at theses critical nodes CN1 and CN2 may vary unexpectedly due to electrical noise caused by coupling effects and/or the general characteristics of the silicon substrate. Consequently, the voltage differential may not be sufficient for the latching device to latch the proper data.
One solution to this problem involves utilizing a separate circuit or logic component to apply an overcompensating differential voltage to the sense amplifier thereby overriding any spurious noise present in the critical nodes CN1 and CN2. Another solution is to utilize a pre-charging device to pre-charge the critical nodes CN1 and CN2 and overdrive any spurious noise that may be present. A third solution is to utilize a separate balancing circuit to balance the voltage levels at these critical nodes so as to negate the effect of any spurious noise that may be present. Unfortunately, all three of these solutions negatively impact the performance of the sense amplifier device by generally making each sense/read operation take longer. In addition, the extra set-up circuitry for pre-charging and/or balancing the critical nodes takes up valuable space on the silicon chip and consequently adds to the cost of any memory device that includes such set-up circuitry. An improved method and system for pre-charging and biasing the critical nodes of a latch-type sense amplifier are desirable.